Special Introduction Future Fab Intl. Volume 32, January 15, 2010
Welcome to this special issue of FFI focused on the revised ITRS. Since the 2009 ITRS is a dynamic document, you will find many exciting new ideas and improvements as compared with the 2007 ITRS version.
Paolo Gargini, Intel Corporation

 INTRODUCTION: Design Implementation & Process Integration Future Fab Intl. Volume 26, July 10, 2008
Increasing process variability at advanced technology nodes of 65nm and beyond has significant impact on design. The paper by Vigyan Singhal of Elastix Corporation points out that enforcing wider design margins to “accommodate” process variability may result in chips with bigger area, lower performance and higher power consumption than could otherwise be produced for a given process technology.
Peter Rabkin, SanDisk Corp.

 INTRODUCTION: Design Implementation & Process Integration Future Fab Intl. Volume 26, July 10, 2008
Designers must continually learn new tricks to manage ever-increasing challenges and exploit new opportunities. As we continue down Moore’s Law, we find ourselves challenged at both ends – the problems of the large, and the problems of the small.
Steven E. Schulz, Silicon Integration Initiative, Inc.

 Leveraging Variability to Increase Chip Performance Future Fab Intl. Volume 26, July 10, 2008
Chip manufacturers typically enforce wide design margins in order to accommodate the effects of variability. This practice results in chips with artificially lower performance and higher power consumption than could otherwise be produced from a given process technology. This article introduces “elastic clocking,” a new concept that offers chip makers a method for leveraging variability to build chips that, on average, operate with faster performance or lower power or both, compared with chips based on conventional “rigid” clocking schemes.
Vigyan Singhal, Elastix Corporation

 SoC Design Requires a New, Predictable Approach Future Fab Intl. Volume 26, July 10, 2008
The design of complex System on Chip (SoC) devices is at a crisis of predictability. Data published recently by EE Times shows that 89 percent of chip designs miss their schedules and that they average being late 44 percent of the time![1] Clearly there is a major problem with the methodology that is being used today.
David Lautzenheiser, Silistix, Inc.

 INTRODUCTION: Design Implementation & Process Integration Future Fab Intl. Volume 24, January 25, 2008
Modern designs have to address numerous issues to be testable, easy to debug and manufacturable with high yield. They also need to comply with performance, power, reliability and other requirements. The paper by Al Crouch of Inovys Corp. focuses mostly on design for test. However, it reviews some of the other requirements broadly described by “DFx” terms, such as design for test (DFT), design for debug (DFD), design for manufacturability (DFM), design for yield (DFY), design for reliability (DFR), and less-well-known terms, such as design for power (DFP), or even design for heat (thermal performance) DFH.
Peter Rabkin, SanDisk Corp.

 The Evolution and Future of DFx in Modern ICs Future Fab Intl. Volume 24, January 25, 2008
In the past Design-for-Test, known as DFT, was the most popular concurrent engineering term in use. However, recent changes in the nature of process tracking, yield analysis and the difficulty of manufacturing has led to a spate of new “Design-for” terms; the most widely used and confused term being DFM, but DFY, DFR, DFD and DFPA have also been used recently.
Al Crouch, ASSET InterTech, Inc.

 INTRODUCTION: Design Implementation & Process Integration Future Fab Intl. Volume 27, October 30, 2008
DFM is developing into the direction of optimizing not only the methodologies, but also associated human and organizational factors.
Peter Rabkin, SanDisk Corp.

 INTRODUCTION: Design Implementation & Process Integration Future Fab Intl. Volume 29, April 29, 2009
Today there is no limitation in the demands to integrate more and more functions on a semiconductor chip. Moore’s Law has supported this advance for decades.
Kazu Yamada, NEC Electronics America, Inc.

 The Shifting Landscape of DFM in the Context of Human Factor Future Fab Intl. Volume 27, October 30, 2008
Design for manufacturability (DFM) means different things to different audiences. From a practical standpoint, DFM involves the communications between the design community and the manufacturing community to ensure that complex chips can be designed, verified and manufactured with short TAT, good yield and minimum cost.
Ching-Yen Ho, Takumi Technology Corp.

 INTRO: Design Implementation & Process Integration Future Fab Intl. Volume 30, July 09, 2009
Modern designs require accounting for a wide variety of process-to-design interactions. Process complexities continue to deepen, and their impact on design robustness and manufacturability is becoming much more pronounced with each subsequent nanoscale technology node. Therefore a wide variety of accurate models that adequately reflect physical complexity of semiconductor processes at different levels of modeling hierarchy have to be developed and implemented within design flows.
Peter Rabkin, SanDisk Corp.

 Simulation to the Rescue of ITRS Roadmap Complexity Future Fab Intl. Volume 29, April 29, 2009
Today’s MOSFETs look like distant cousins of the MOSFETs we studied at university a mere decade ago. Far from simple scaled versions of previous designs, they feature silicon germanium embedded in raised source and drain regions, high-k gate dielectrics and, in a curious revivalist twist, metal gates.
Synopsys Business Development, Synopsys

 Era of ‘Hybrid’ in DFM? Future Fab Intl. Volume 27, October 30, 2008
With the recent and steep increase in energy costs and the public’s rapidly growing awareness of global warming, high tech industries are now busily working to develop green energy technologies. One such technology, which has successfully been put into practical use in hybrid vehicles, combines an electric motor with a traditional fossil fuel engine and makes both “motors” operate collaboratively to save gas. However, how they collaborate is very interesting and somewhat different depending on the automotive manufacturer who produces them. The most popular method is to let the electric motor assist the gas engine in the lower-revolution stage, when the gas engine is relatively weak and the electric motor can offer strong torque. Once the engine’s revolution reaches a speed high enough to generate large torque with good efficiency, the gas engine can be used as the primary source of power. This is one interesting example of a technology that has been implemented to achieve an ultimate goal.
Kazu Yamada, NEC Electronics America, Inc.

 INTRODUCTION: Design Implementation & Process Integration Future Fab Intl. Volume 25, April 30, 2008
As old-timers know, mask making used to be a “no-brainer” and a straightforward process in IC manufacturing, up until 130nm. This last stage of design used to take no longer than a few days and cost a fraction of overall design and manufacturing expenses. However, when engineers began attempting to design geometries smaller than 100nm on silicon – with a 248 or 193nm wavelength – making masks became the equivalent of using an axe to craft fine pieces of woodwork! Another limitation for Moore’s law!
Kazu Yamada, NEC Electronics America, Inc.

 Open Modeling Interface: An Open API for Modeling Future Fab Intl. Volume 30, July 09, 2009
A proposal of an alternative architecture to the current widespread use of embedded models within applications. The Open Model Interface (OMI) allows the separation of any given model from its application by using the OMI as the interface between the model (provider) and the application (consumer).
Sumit DasGupta, Silicon Integration Initiative, Inc., Nick English, Silicon Integration Initiative, Inc., Stacy Doss, Silicon Integration Initiative, Inc.

 Approaching 2X Technology Node(s): Lithography, OPC and DFM Options for Manufacturable Designs Future Fab Intl. Volume 29, April 29, 2009
A look at approaches that will allow the realization of 2X technology node devices with reasonable yield and cost.
Soichi Inoue, Toshiba Corporation

 It Takes a Village to Reduce Mask Costs Future Fab Intl. Volume 25, April 30, 2008
There is an old proverb that says, “It takes a village to raise a child.” The gist is that it takes a collaborative effort among different players to make a difference. Three very different companies from the design, photo-mask and equipment spaces are applying the proverb to create a virtual village to tackle costs.
Mitchell Heins, Pyxis Technology, Inc., Christopher Progler, Photronics Inc., Venu Vellanki, KLA-Tencor

 INTRODUCTION: Design Implementation & Process Integration Future Fab Intl. Volume 32, January 15, 2010
The proclamation "make things as simple as possible ... but no simpler" seems relevant in light of the next two articles. While design needs have always stretched the current boundaries of the day, today there is truly less headroom for suboptimal designs.
Steven E. Schulz, Silicon Integration Initiative, Inc.

 INTRO: Design Implementation & Process Integration Future Fab Intl. Volume 31, October 29, 2009
As the industry embraces global design teams and a multitude of IP providers, the need for simulation consistency becomes even more critical. How many times have we been surprised by the assumptions that a third party made in defining a “worst case” simulation condition? In addition, as we see effects such as temperature inversion in delay characteristics, it becomes more dangerous to rely on our intuition to predict how a circuit was characterized.
Liam Madden, Xilinx Inc

 3D Stacked Silicon Using Through Silicon Via Future Fab Intl. Volume 29, April 29, 2009
A presentation of alternative 3D technologies, emphasizing the benefits of through silicon via, as well as prediction of future trends of 3D regarding partitioning, placement and stack growth.
Roger Carpenter, Javelin Design Automation

 INTRODUCTION: Design Implementation & Process Integration Future Fab Intl. Volume 28, January 15, 2009
A perpetual challenge in the field of Design is that, unlike many manufacturing areas, it is more difficult to associate any specific measurable need to any specific target year of introduction.
Steven E. Schulz, Silicon Integration Initiative, Inc.

 eDFM – Not “If” It Will Print, But “How”? Future Fab Intl. Volume 25, April 30, 2008
Electrical Design for Manufacturing (eDFM) is an emerging field of technology that asserts to predict how a circuit will behave as modified by distortions in the manufacturing process. While the original work in DFM was centered on lithography, eDFM goes further to predict and optimize the effects on power and performance of chip designs. This article provides an introduction to eDFM and an abbreviated canvas of the available tools in the market.
Randy Smith, Randysan Consulting

 Liberty Syntax Extensions for Characterization and Validation Future Fab Intl. Volume 31, October 29, 2009
Why including a certain specification for characterization setup data in every Liberty Library File is a value-add.
Sumit DasGupta, Silicon Integration Initiative, Inc., Nick English, Silicon Integration Initiative, Inc.

 Simulation to the Rescue of ITRS Roadmap Complexity Future Fab Intl. Volume 28, January 15, 2009
By now it is no secret that CMOS technology is increasingly reliant on new materials and structural innovations to achieve the International Technology Roadmap for Semiconductors (ITRS) performance targets. Yet, with the new materials and structures, the number of process and architectural choices increase, raising the complexity and cost of the technology development effort.
Synopsys Business Development, Synopsys

 Modeling & Simulation Future Fab Intl. Volume 32, January 15, 2010
A paper describing the changes compared to the 2008 chapter, as well as difficult and long-term challenges for the Modeling & Simulation chapter of the ITRS.
Jürgen Lorenz, Fraunhofer Institute of Integrated Systems and Device Technology (IISB)

 Modeling & Simulation Future Fab Intl. Volume 28, January 15, 2009
A review of the difficult challenges, main trends as well as cost and time reduction projects for the ITRS’ Modeling & Simulation chapter.
Jürgen Lorenz, Fraunhofer Institute of Integrated Systems and Device Technology (IISB)

 Profile: Atrenta Future Fab Intl. Volume 32, January 15, 2010

Atrenta Business Development, Atrenta

 The Power of Early Design Closure® Future Fab Intl. Volume 28, January 15, 2009
Atrenta® is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow.
Atrenta Business Development, Atrenta

 Design and System Drivers Future Fab Intl. Volume 32, January 15, 2010
A look at the challenges and required solutions, as well as the new aspects, in the Design and System Drivers Chapters of the 2009 ITRS.
Juan-Antonio Carballo, IBM VC Group, Andrew B. Kahng, University of California, San Diego

 Design and System Drivers Future Fab Intl. Volume 28, January 15, 2009
A look at the key challenges, industry drivers, recent progress as well as plans for 2009 for the Design and System Drivers chapters of the ITRS.
Juan-Antonio Carballo, IBM VC Group, Andrew B. Kahng, University of California, San Diego

 Introduction: Design Implementation & Process Integration Future Fab Intl. Volume 33, April 27, 2010
Moving into the 3rd dimension may allow extending Moore's Law beyond traditional geometry scaling. The effective scaling can be achieved, for instance, by TSV 3D-stacked integration – a new direction in the semiconductor industry.
Peter Rabkin, SanDisk Corp.

 Analysis of the Communication Architecture in 3D ICs: Physical Models of TSVs Future Fab Intl. Volume 33, April 27, 2010
Why the design of the communication architecture according to the physical characteristics of TSVs is key to maximizing potential 3D IC performance benefits.
Lancaster University