Special Introduction Future Fab Intl. Volume 32, January 15, 2010
Welcome to this special issue of FFI focused on the revised ITRS. Since the 2009 ITRS is a dynamic document, you will find many exciting new ideas and improvements as compared with the 2007 ITRS version.
Paolo Gargini, Intel Corporation

 INTRODUCTION: Front End of Line Future Fab Intl. Volume 26, July 10, 2008
Lithography as a key patterning process in semiconductor manufacturing faces difficult challenges at ever-smaller dimensions. Extreme ultraviolet (EUV) lithography is considered a potential solution in the future. The International Roadmap for Semiconductors emphasizes line width roughness (LWR), sensitivity and resolution as key EUV resist issues. However, the interdependence between those characteristics makes material optimization extremely difficult.
Ernst Richter, Inotera Memories / Qimonda

 INTRODUCTION: Front End of Line Future Fab Intl. Volume 26, July 10, 2008
Technology development in the semiconductor industry presents many challenges for the engineer trying to optimize many interdependent process parameters. Engineers have long had to deal with trade-offs such as uniformity and throughput, defect levels and PM frequency, reliability and queue time.
John Caffall, Spansion Inc.

 Production-Ready Immersion Scanners Future Fab Intl. Volume 26, July 10, 2008
Immersion lithography has transitioned from the research and development phase to volume manufacturing in record time. The Nikon NSR-S610C immersion scanner is already being used in high-volume manufacturing around the world. There is a variety of key performance criteria that must be met for immersion lithography to be successful in manufacturing. Production- ready immersion scanners must deliver high productivity on a reliable platform, consistently providing excellent overlay and imaging performance, while achieving low defectivity levels. The design of the immersion scanner plays a pivotal role in satisfying these production-readiness requirements.

 Resolution, Line Width Roughness and Sensitivity in Advanced Photoresists Future Fab Intl. Volume 26, July 10, 2008
The fundamental relationship between resolution, line width roughness and sensitivity makes it extremely challenging to optimize photoresists for those three characteristics simultaneously. A figure of merit has been designed to measure true photoresist progress in this respect. This article shows how the figure of merit KLUP allows direct and quantitative comparison between different routes targeting the best combination of improved resolution, reduced line width roughness and increased sensitivity.
NXP Semiconductors

 INTRODUCTION: Front End of Line Future Fab Intl. Volume 24, January 25, 2008
As semiconductor technology moves to ever-smaller geometries, from 65nm to 45nm to 32nm and beyond, the challenges of fabrication seem to grow exponentially greater. The processing material characteristics that are required and the ability to define patterns in the circuits present problems of great magnitude, yet at the same time so subtle in nature as to be daunting even to the highly skilled engineers in the industry.
John Caffall, Spansion Inc., Ernst Richter, Inotera Memories / Qimonda

 45nm Lithography – It’s All About the Lens Future Fab Intl. Volume 24, January 25, 2008
Defectivity has been a key area of focus for immersion lithography. As IC manufacturers move into production with acceptable defectivity levels, the scanner lens design becomes a critical factor for 45nm half-pitch manufacturing and beyond. New catadioptric lenses use refractive and reflective components to satisfy the numerical aperture requirements. However, minimized aberrations, low levels of flare and apodization, as well as efficient polarization control are all necessary to satisfy the stringent imaging requirements for these advanced immersion applications.
Christopher Sparkes, Nikon , H. Magoon, Nikon , Tomoyuki Matsuyama, Nikon Corporation

 Stacked Metal Gate Electrodes: Source for FEOL Galvanic Corrosion? Future Fab Intl. Volume 24, January 25, 2008
The use of stacked metal gate electrodes in future transistors creates a risk for galvanic corrosion during cleaning and etching. The influence of metal choice, integration scheme and characteristics of the cleaning mixture is considered.
Sylvain Garaud, imec, Rita Vos, imec, Paul Mertens, imec

 When Other Graphite Materials Hit the Wall, Poco Graphite Breaks Through Future Fab Intl. Volume 24, January 25, 2008
Poco Graphite manufactures specialty graphites and silicon carbide with custom machining capabilities for OEMs and fabs.

 INTRODUCTION: Front End of Line Future Fab Intl. Volume 29, April 29, 2009
Spring is here. In our fond memories of springs past, designers would pull out their Moore’s Law calculators, with their single “0.7x” button, to define patterning requirements for the next node. Stepper designers would grow the lens numerical aperture to an “impossible” 0.54, process engineers would tweak the resist and etch processes, and the job would be done.
Janice M. Golda, Intel Corporation

 INTRODUCTION: Front End of Line Future Fab Intl. Volume 27, October 30, 2008
The ITRS emphasizes the importance of “material-limited device scaling” for the future front-end processes. Integration of diverse new materials and device architectures are the key challenges. Lithography cost control is another critical issue, and imprint lithography is named as a potential next-generation option.
Ernst Richter, Inotera Memories / Qimonda

 INTRO: Front End of Line Future Fab Intl. Volume 30, July 09, 2009
This issue features two papers from opposite ends of the lithography R&D spectrum.
John Warlaumont, SEMATECH

 INTRODUCTION: Front End of Line Future Fab Intl. Volume 29, April 29, 2009
Continued dimensional scaling will require either EUV lithography (very promising, yet still very challenging) or getting more from the available optical scanners, most likely with multiple exposures.
John Warlaumont, SEMATECH

 Addressing Critical Challenges with New Materials and Device Architectures for Future-Generation CMOSFETs Future Fab Intl. Volume 27, October 30, 2008
Scaling of CMOS for enhancing performance and reducing costs is facing numerous fundamental challenges that can only be addressed with the introduction of new materials and/or novel device architectures. Research on new materials for front-end CMOS has focused primarily on gate stack (high-k/metal gates), novel silicides and alternative high-mobility channels. While novel materials for gate stack (replacing SiO2) and silicides (doping/alloying NiSix) have been introduced into production, evaluation of high-mobility channels is still in the research phase. Ge-based materials are attractive for potential use in future generation pMOSFET because of their high hole mobility. From the novel device architecture standpoint, promising scaled non-planar devices (FinFET/Tri-gates) have been demonstrated in the research phase, despite significant module and process integration challenges. This article will briefly discuss one of many critical challenges in Ge-based channels (i.e., threshold voltage control) and also provide an overview of module-level issues in non-planar devices.
Jungwoo Oh, SEMATECH, Hemant Adhikari, SEMATECH, Casey Smith, SEMATECH, H. Rusty Harris, SEMATECH, Prashant Majhi, SEMATECH, Raj Jammy, SEMATECH

 INTRODUCTION: Front End of Line Future Fab Intl. Volume 25, April 30, 2008
The continued march to shrink feature sizes to double density every two years has enabled the industry to realize Moore’s law. As feature dimensions continue to scale, a number of previously insignificant factors are becoming increasingly important to control in order to deliver high product performance at high yields. Keeping reticles defect free over their life cycle has always been essential to delivering high yields, as a single printable reticle defect can affect every die on every wafer if not caught. In this issue of Future Fab International, you will find a thought-provoking paper on a new consideration for managing reticles over the reticle life cycle.
Janice M. Golda, Intel Corporation

 INTRO: Front End of Line Future Fab Intl. Volume 31, October 29, 2009
Delivering semiconductor products compelling to the consumer demands acute attention to detail. In this issue of Future Fab International, you will find two papers that at a cursory level cover seemingly unrelated topics, but at a deeper level share this penchant for detail. The details lie in the materials science and analytical modeling techniques used to optimize products and processes for today’s market.
Janice M. Golda, Intel Corporation

 PROFILE: Swagelok Future Fab Intl. Volume 30, July 09, 2009
Swagelok Company understands the need for a collaborative process, and examples of the company's commitment to those important factors can be found in its newest technology products.
Swagelok Business Development, Swagelok Company

 Build Your Future With Nikon Future Fab Intl. Volume 29, April 29, 2009
From high-throughput i-line steppers to advanced immersion ArF scanners for 32nm applications and beyond, Nikon delivers superior performance with the lowest cost of ownership and the most comprehensive customer support of any manufacturer.
Nikon Business Development, Nikon

 Extending the Roadmap With Step and Flash Imprint Lithography Future Fab Intl. Volume 27, October 30, 2008

 EFM: A Pernicious Threat to Reticles – Exposed Future Fab Intl. Volume 25, April 30, 2008
In Issue 22, a brief overview was given of the changing nature of reticle electrostatic damage, and the consequences for semiconductor fabs were discussed. The conclusions in that review were based on the interpretation of many pieces of evidence taken from different sources, but the risk assessment was empirical, so has not yet been widely accepted. This article presents new data from an experiment that was designed to quantify the damage effects under closely controlled conditions.
Gavin Rider, Microtome

 SAFC Hitech Future Fab Intl. Volume 31, October 29, 2009
Changing the Face of Materials Technology
SAFC Hitech

 How to Save Over $100M Per Year on Lithography Cost Future Fab Intl. Volume 30, July 09, 2009
How a specific high-throughput approach regarding maskless electron beam lithography can save IC manufacturers over $100 million per year on costs.
Bert Jan Kampherbeek, MAPPER Lithography B.V., The Netherlands, Marco Wieland, MAPPER Lithography B.V., The Netherlands

 Resist Removal and Cleaning for TANOS Metal Gate Nonvolatile Memories Future Fab Intl. Volume 30, July 09, 2009
A description of a new wet chemical approach for resist removal and cleaning that has been developed using hot, 150ºC, H2SO4 with very low levels of H2O2 followed by diluted NH4OH.
Enrico Bellandi, Numonyx Development Center, Italy , Cinzia De Marco, Numonyx Development Center, Italy , Antonio Truscello, FSI International, Jeffery W. Butterbaugh, FSI International

 Double Patterning Lithography: Reducing the Cost Future Fab Intl. Volume 29, April 29, 2009
A paper describing process flows, steps and materials, regarding cost, line roughness, overlay and critical dimension uniformity regarding double patterning lithography for the 32nm technology node.
Andy Miller, imec, Jan Provoost, imec, Mireille Maenhoudt, imec

 Extending the Roadmap With Step and Flash Imprint Lithography Future Fab Intl. Volume 27, October 30, 2008
Imprint lithography has emerged recently as a leading candidate for extending and complementing optical lithography in semiconductor memory applications where high resolution and feature density must be accomplished cost-effectively. The advantages of Step and Flash Imprint Lithography (S-FIL®) make it uniquely capable for nonvolatile memory (NVM) applications at the 2xnm nodes. Progress in throughput, overlay and defectivity was demonstrated and will be reported.
Douglas J. Resnick, Molecular Imprints, Inc., C. Mark Melliar-Smith, Molecular Imprints, Inc., S.V. Sreenivasan, Molecular Imprints, Inc., Ben Eynon, Molecular Imprints, Inc.

 When Other Graphite Materials Hit the Wall, Poco Graphite Breaks Through Future Fab Intl. Volume 25, April 30, 2008
Poco Graphite manufactures specialty graphites and silicon carbide with custom machining capabilities for OEMs and fabs.

 A Model for the Bilayer Resist Dry Development Future Fab Intl. Volume 31, October 29, 2009
A brief study on bilayer resist development performed using an Ar/O2 plasma in a dual frequency diode-reactor.
Giuseppe Garozzo, Numonyx Development Center, Italy , Antonino La Magna, CNR-IMM, Italy , Costanza Bellecci, Numonyx Development Center, Italy , Nicola Nastasi, Numonyx Development Center, Italy

 An Engineering Model of the C4F8/O2/Ar Chemistry in the Dry Etching of SiO2 Future Fab Intl. Volume 29, April 29, 2009
A presentation of a zero-dimensional dry etching model that can link the average etching performance to the main engineering/equipment parameters, particularly one that enables the calculation of the polymer coverage as a function of the gas flow.
Giuseppe Garozzo, Numonyx Development Center, Italy , Antonino La Magna, CNR-IMM, Italy , Stefano Colombo, ST-Microelectronics, Italy

 Facing the Industry's Discrete Solution Change Future Fab Intl. Volume 27, October 30, 2008

 Sealing in Success: The Role of Perfluoroelastomer Seals in Advanced IC Production Future Fab Intl. Volume 31, October 29, 2009
Why increasing the industry’s understanding of available sealing solutions and how they are best used with various new materials can go a long way in helping to bring advanced manufacturing processes online more quickly and efficiently.
Fred Freerks, Fred Freerks Consulting, Dalia Vernikovsky, Applied Seals North America, Inc.

 INTRODUCTION: Front End of Line Future Fab Intl. Volume 28, January 15, 2009
Looking back at how the ITRS began, we have to reference Gordon Moore’s 1965 original publication in Electronics magazine.
John Caffall, Spansion Inc.

 Ultrathin Barrier/Seed Layers: Challenges of Scaling for Future Copper Interconnect Future Fab Intl. Volume 25, April 30, 2008
This article explores the scaling trends and subsequent process technology advances in ultrathin barrier/seed layers for Cu interconnect.
Jeff Catlin, ATMI, Inc., Jeff Roeder, ATMI, Inc., Bryan C. Hendrix, ATMI, Inc.

 INTRODUCTION: Front End of Line Future Fab Intl. Volume 32, January 15, 2010
In this Front End of Line section, we have a first look at the 2009 ITRS lithography and front end technology materials; good summaries to get us a quick outlook for the next few years.
John Schmitz, NXP Semiconductors

 Build Your Future With Nikon Future Fab Intl. Volume 28, January 15, 2009
Nikon is a worldwide leader in lithography equipment for the microelectronics manufacturing industry, with more than 7,800 exposure systems installed worldwide.
Nikon Business Development, Nikon

 Profile: Nikon Future Fab Intl. Volume 32, January 15, 2010

Nikon Corporation

 Lithography Future Fab Intl. Volume 28, January 15, 2009
A look at the roadmap evolution, gate scaling and CD uniformity, as well as memory and logic requirements and the outlook for the Lithography area of the ITRS.
Michael Lercel, IBM

 Lithography Future Fab Intl. Volume 32, January 15, 2010
A paper that details the cost of ownership and describes the difficult challenges regarding the Lithography Chapter of the ITRS.
Greg Hughes, SEMATECH

 SAFC Hitech: Changing the Face of Materials Technology Future Fab Intl. Volume 28, January 15, 2009
A look at the roadmap evolution, gate scaling and CD uniformity, as well as memory and logic requirements and the outlook for the Lithography area of the ITRS.
SAFC Hitech Business Development, SAFC Hitech

 Profile: SAFC Hitech Future Fab Intl. Volume 32, January 15, 2010

SAFC Hitech

 Front End Processes Future Fab Intl. Volume 28, January 15, 2009
A look at the roadmap evolution, gate scaling and CD uniformity, as well as memory and logic requirements and the outlook for the Lithography area of the ITRS.
Jeffery W. Butterbaugh, FSI International, Lawrence Larson, Texas State University at San Marcos, TX, Raj Jammy, SEMATECH

 Front End Processes Future Fab Intl. Volume 32, January 15, 2010
A forecast of scaling-driven technology requirements and potential solutions is provided for each of the technology areas in the FEP chapter of the ITRS.
Jeffery W. Butterbaugh, FSI International, Lawrence Larson, Texas State University at San Marcos, TX, Raj Jammy, SEMATECH

 Introduction: Front End of Line Future Fab Intl. Volume 33, April 27, 2010
And the beat goes on ... the beat of Moore's Law, that is. In this issue of Future Fab International, you will find two different perspectives on "what’s next" and "what's after what’s next" in lithography, as each author examines different approaches to continue the seemingly endless drumbeat of reducing feature sizes to help enable new applications for technology. Both papers share a second common theme in illustrating various roles of consortia in helping to continue the drumbeat.
Janice M. Golda, Intel Corporation

 The IMAGINE Program: Development of and Prospects for the MAPPER Maskless Technology Future Fab Intl. Volume 33, April 27, 2010
A description of the first large-scale industrial program having the objective of developing a viable maskless lithography solution from tool to infrastructure.
Serge Tedesco, CEA-Leti, Laurent Pain, CEA-Leti, David Rio, CEA-Leti, Bert Jan Kampherbeek, MAPPER Lithography B.V., The Netherlands

 Section Sponsor – SAFC Future Fab Intl. Volume 33, April 27, 2010
Materials science continues to play a fundamental role in the ongoing evolution of the semiconductor industry, as consumers demand enhanced functionality in smaller footprints.
SAFC Hitech

 Pushing Lithography to Its Limits Future Fab Intl. Volume 33, April 27, 2010
Why innovative use of new materials, transistor architectures and lithographic techniques are key research topics for today’s semiconductor industry.
Kurt Ronse, imec