Special Introduction Future Fab Intl. Volume 32, January 15, 2010
Welcome to this special issue of FFI focused on the revised ITRS. Since the 2009 ITRS is a dynamic document, you will find many exciting new ideas and improvements as compared with the 2007 ITRS version.
Paolo Gargini, Intel Corporation

 Diagnosing the ‘Undiagnosable’ Faults Future Fab Intl. Volume 26, July 10, 2008
The manufacturing of complex IC devices is becoming more dependent on determining and solving factors that contribute to excessive yield loss. Analyzing the root cause results of electrical failures during test is now recognized as an emerging industry need. Fortunately, structural test using DfT in the IC design can facilitate this. The general perception has been that this is accomplished by just capturing all of the scan failures and logging the raw data to a file for subsequent analysis by an off-line diagnostic tool.
Phil Burlison, Verigy

 Effect of Cu Contents on Electromigration Reliability of Flip-chip Solder Joints Future Fab Intl. Volume 26, July 10, 2008
Observations from assorted current stressing experiments on flip-chip solder joints imply that the Cu content in a solder joint system plays a dominant role in its electromigration reliability. In this paper, electromigration reliability of various flip-chip solder joint systems, including different substrate pad finishes and solder compositions, is summarized to demonstrate the effect of the Cu content. A unified failure mechanism is proposed based on morphologies observed in the current-stressed solder joints with different substrate pad finishes and different solder compositions.
Yi-Shao Lai, Advanced Semiconductor Engineering, Inc.

 INTRODUCTION: Assembly, Test & Packaging Technologies Future Fab Intl. Volume 26, July 10, 2008
Electronics are all around us, from the multitasking cell phone to the many products around the home, the office and the car that depend upon electronics for operation. So, what does the future hold? From the assembly, test and packaging engineering perspective, the rapid evolvement and development of new ideas and new technologies have been nothing short of astounding.
William (Bill) T. Chen, ASE (U.S.) Inc.

 INTRODUCTION: Assembly, Test & Packaging Technologies Future Fab Intl. Volume 24, January 25, 2008
Welcome to 2008, the year of many changes and challenges in the electronic industry. How to address the requirements outlined in the REACH documents, finalizing the remaining issues with the Pb-free conversion, and ramping production on extremely complex products are just some of the issues that must be resolved before the end of 2008.
Steve Greathouse, Plexus Corporation

 Edge Silicon Via (ESV) Technology for 3D Wafer-Level CSP Future Fab Intl. Volume 24, January 25, 2008
Shrinking size and growing demand for portable electronic devices are driving 3D packaging needs. TSV (through silicon via) has attracted much attention, but TSV is not yet a cost-effective manufacturing option. An edge silicon via (ESV) 3D stacking technology is described which provides an HVM, low-cost alternative that extends the life of existing fabrication infrastructure by providing a back-end, packaging-based solution for increased component densities.
Marc Robinson, Vertical Circuits, Inc

 Open ATE: An Architecture for the Future Future Fab Intl. Volume 24, January 25, 2008
For years analysts have been saying the semiconductor test industry is too small to support the current number of automatic test equipment (ATE) vendors. Profitability of ATE vendors, as a group, has been minimal. Customers are looking for the next big cost-of-test-reduction project. Consolidation from today’s 25-30 proprietary testers to two or three open architecture testers would substantially reduce the industry’s overall costs to develop new test capabilities. It’s time to go to the next level in industry collaboration.
Paul Roddy, Freescale Semiconductor

 INTRODUCTION: Assembly Test & Packaging Technologies Future Fab Intl. Volume 29, April 29, 2009
Many companies in the industry are carefully husbanding their resources for investment in research and development, in preparation for inevitable economic upturn and market resurgence. In recent years, there have been great advancements in innovation and invention of electronics products, largely driven by the imperatives of the expanding consumer market.
William (Bill) T. Chen, ASE (U.S.) Inc.

 For SIPs, Concurrent RF Testing Delivers Advantages in Cost-of-Test and Quality of Results Future Fab Intl. Volume 29, April 29, 2009
This paper that describes what RF testing is and why it matters also explains why the benefits include more-accurate and realistic testing, along with higher throughput.
Keith Schaub, Advantest

 INTRO: Assembly Test & Packaging Technologies Future Fab Intl. Volume 31, October 29, 2009
As microprocessors, RF devices and a multitude of other performance-enhanced products get faster with more functionality, the thermal dissipation requirements continue proportionally.
Steve Greathouse, Plexus Corporation

 INTRO: Assembly, Test & Packaging Technologies Future Fab Intl. Volume 30, July 09, 2009
Flip chip has been in production for decades. The design and implementation of flip chip requires the successful convergence of three technologies: wafer bumping, flip chip assembly and substrate. Among the three technologies, the critical importance of substrate is probably least appreciated and understood, although it is often a large, if not the largest, contributor to the flip chip packaging cost.
William (Bill) T. Chen, ASE (U.S.) Inc.

 Cool Under Pressure, While Solving the Pump-Out Problem Future Fab Intl. Volume 31, October 29, 2009
A paper describing a material that helps engineers and package designers solve complex thermal management problems.
Sara Paisner, LORD Corporation

 The Road to 4th-Generation fcCSP Substrates Future Fab Intl. Volume 30, July 09, 2009
A look at how taking a holistic approach to flip-chip chip scale packaging can lead to development of a low-cost, very high-volume product.
Bernd Appelt, ASE (U.S.) Inc.

 INTRODUCTION: Assembly, Test & Packaging Technologies Future Fab Intl. Volume 25, April 30, 2008
New technologies are the lifeblood of the electronics industry. Engineers with their “out of the box” thinking are working on leading-edge pathfinding projects that create significant changes in the way the industry does things. Revolutionary advances change the direction of a technology, while evolutionary advances refine the current state of the art to a better level.
Steve Greathouse, Plexus Corporation

 INTRODUCTION: Assembly, Test & Packaging Technologies Future Fab Intl. Volume 27, October 30, 2008
Moore’s law is still continuing to guide the industry, but many new and challenging ways are being developed to be able to meet its demands. Stacked packages (POP), stacked die, various types of MCMs and the use of through silicon vias (TSVs) to interconnect die stacked tightly together are just a few of the packaging and assembly options being considered to keep up with Moore’s complexity forecast.
Steve Greathouse, Plexus Corporation

 The Occam Process: Solderless Assembly and Interconnection of Electronic Packages Future Fab Intl. Volume 25, April 30, 2008
This article will describe details of what has come to be known as the Occam Process, so named to honor the 14th-century English philosopher and logician, William of Occam, whose rigorous thinking and arguments favored and encouraged the finding of the simplest possible solution to every problem.
Joseph Fjelstad, Verdant Electronics

 Evolution and Revolution in IC Assembly Future Fab Intl. Volume 27, October 30, 2008
Over the years, the contribution of packaging to the overall product cost has significantly increased. Ten years ago, the die was still the dominant factor in product cost, with it, in many cases, making up 70 percent of the cost. Due to the further miniaturization in wafer fab processes via Moore’s Law on the one hand, and the more-complex products to support system solutions to the OEM on the other hand, today the die usually makes up less than 50 percent of the total product cost, and assembly can constitute 50 percent or more. This results in an even greater focus on cost-effective packaging solutions.
Eef Bagerman, NXP Research

 INTRODUCTION: Assembly, Test & Packaging Technologies Future Fab Intl. Volume 28, January 15, 2009
Future needs drive present-day strategies for worldwide research and development among manufacturers’ research facilities, universities and national labs.
Steve Greathouse, Plexus Corporation

 Verigy – We Innovate, Collaborate, Transform and Deliver… Results You Can Count On. Future Fab Intl. Volume 28, January 15, 2009
The world’s leading semiconductor companies look to Verigy for test solutions that make their innovations possible. We enable our customers to deliver the advanced technology that transforms our world through state-of-the-art computing, communications and consumer electronics products.
Verigy Business Development, Verigy

 INTRODUCTION: Assembly Test & Packaging Technologies Future Fab Intl. Volume 32, January 15, 2010
The ITRS has been repeating the mantra “More than Moore” for the last couple of years and pursuing ways to show the avenues that will make it happen. One of the main methods through which this will happen is by going vertical (Z-Axis) with the packaging.
Steve Greathouse, Plexus Corporation

 ITRS CHAPTER: Test & Test Equipment Future Fab Intl. Volume 28, January 15, 2009
A look at the drivers, key trends and directions for the Test area within the ITRS roadmap.
Roger Barth, Numonyx

 Profile: Advantest Future Fab Intl. Volume 32, January 15, 2010

 Assembly & Packaging Future Fab Intl. Volume 28, January 15, 2009
An overview of the innovations, emerging technologies and difficult challenges regarding the Assembly & Packaging chapter of the ITRS.
W. R. Bottoms, Third Millennium Test Solutions, Inc., William (Bill) T. Chen, ASE (U.S.) Inc.

 Test & Test Equipment Future Fab Intl. Volume 32, January 15, 2010
A look at the most significant updates to the ITRS Test chapter, including 3D silicon devices, adaptive test and a summary of the key findings of a cost of test survey.
Roger Barth, Numonyx

 Assembly & Packaging Future Fab Intl. Volume 32, January 15, 2010
This paper overviews the changes that occurred for the Assembly & Packaging Chapter since the 2008 Roadmap, specifically involving System in Package, 3D Integration, Wafer-Level Packaging, MEMS, Optical Devices and Automotive Electronics.
W. R. Bottoms, Third Millennium Test Solutions, Inc.

 Introduction: Assembly Test & Packaging Technologies Future Fab Intl. Volume 33, April 27, 2010
3D has arrived. And is here to stay, by becoming increasingly prevalent in blockbuster movies, medical appliances and electronics. 3D integrations, whether on device and/or package levels, have been subjects of vigorous research and development across the industry, academia and research institutes worldwide. While the challenges for 3D are daunting, the promise for 3D provides great possibility for significant advances in both More Moore and More than Moore from speed, bandwidth and power reduction to miniaturization and integration of disparate devices including logic, memory and sensors.
William (Bill) T. Chen, ASE (U.S.) Inc.

 Driving 3D Chip and Circuit Board Test Into High Gear Future Fab Intl. Volume 33, April 27, 2010
A detailed look at what will transpire in the marketplace for embedded instrumentation tools for single-die chips, complex SoCs, multiple-die 3D chips, circuit boards and systems.
Al Crouch, ASSET InterTech, Inc.