In this issue:
Future Visions & Current Concerns
 INTRODUCTION: Future Visions & Current Concerns :: Download the new issue now!
These past few years, a lot of study and work has gone into 3D ICs. But we are nearing the point where this technology will be taken to production, and we will have to narrow down the options, and define what we mean when we talk about a 3D IC. Talking about standards, that will be the first task.
Gilbert Declerck, imec
A Need for Standards in 3DIC :: Download the new issue now!
An article describing why standards are needed in the 3D interconnect circuit arena.
Andrew C. Rudack, SEMATECH, Albany, NY, Jerry Mase, SEMATECH (College of Nanoscale Science and Engineering assignee), Albany, NY
New Technologies & Device Structures
INTRODUCTION: New Technologies & Device Structures :: Download the new issue now!
The emerging 3D IC technology using TSVs seems especially suited to implement many-core ICs. But an important challenge will be the physical and logical implementation of power-efficient core-to-core communication that satisfies the very high bandwidth requirements for such future systems.
Lode Lauwers, imec
3D Connectivity for Many-Core Architectures :: Download the new issue now!
A description of a range of solutions to the 3D many-core connectivity gap that can enable new functionalities for digital and mixed-signal many-core architectures.
Robert E. Geer, College of Nanoscale Science and Engineering, University at Albany, Tom T. Jing, College of Nanoscale Science and Engineering, University at Albany, Michael Liehr, College of Nanoscale Science and Engineering, University at Albany, Wei Wang, College of Nanoscale Science and Engineering, University at Albany
Performance of Scalable 3D On-Chip Networks Architecture: A Comparative Analysis :: Download the new issue now!
An investigation of performance benefits of 3D regarding latency and throughput for such applications as many-core architecture.
Awet Yemane Weldezion, KTH Royal Institute of Technology , Roshan Weerasekera, Lancaster University, Dinesh Pamunuwa, Lancaster University, Hannu Tenhunen, KTH Royal Institute of Technology
Chip Architecture & Integration
INTRODUCTION: Chip Architecture & Integration :: Download the new issue now!
Today the semiconductor industry’s biggest challenge threatening progress is the rapidly increasing power dissipation of ICs and systems. As a result, semiconductor companies are increasingly reviewing "2D SoC" roadmaps and contemplating how and when they must transition to a new paradigm to continue meeting customer demands for smarter, faster, lower-power and lower-cost ICs and systems.
Lisa Tafoya, GSA
Signaling Conventions for Through Silicon Vias in 3D Integrated Circuits :: Download the new issue now!
A discussion of the electrical properties of the TSV, providing insightful performance comparisons between several industry-standard driver circuits to identify signaling conventions for future 3D ICs.
Matt Grange, Lancaster University, Roshan Weerasekera, Lancaster University, Dinesh Pamunuwa, Lancaster University
3D Integration Opportunities for Memory Interconnect in Mobile Computing Architectures :: Download the new issue now!
A review of existing memory interfaces and a demonstration that they need to evolve to new protocols to achieve terabyte-per-second bandwidth with reasonable power consumption.
Denis Dutoit, CEA-Leti MINATEC, Ahmed Jerraya, CEA-Leti MINATEC
Design Implementation & Process Integration
INTRODUCTION: Design Implementation & Process Integration :: Download the new issue now!
The promise of 3D chip stacking is indeed huge, revolutionizing the ability to optimize technology choices to meet optimum performance, power and cost. However, chip stacking stresses multiple levels of the existing supply chain, potentially requiring multiple foundries to supply silicon to an OSAT in order to create a finished stacked product. This significantly complicates the existing issues.
Liam Madden, Xilinx Inc
SmartSamples: Lowering Integration Risks for 3D TSV Products :: Download the new issue now!
A description of a method of validating 3D stacks before the actual product design.
Jan Provoost, imec, Geert Van der Plas, imec, Pol Marchal, imec
Manufacturing, Systems & Software
INTRODUCTION: Manufacturing, Systems & Software :: Download the new issue now!
In this issue, we further explore the discussion from the last issue that introduced Enhanced Equipment Quality Management (EEQM) and its role in unifying efforts to drive systematic characterization and improvement of equipment quality and performance issues among all the requisite players.
Thomas Sonderman, GLOBALFOUNDRIES
Eight Things You Should Know About EEQA (Enhanced Equipment Quality Assurance) :: Download the new issue now!
An article highlighting for industry stakeholders the Enhanced Equipment Quality Assurance initiative’s requirements and potential impacts.
Shigeru Kobayashi, Renesas Technology Corporation, Gino Crispieri, International SEMATECH Manufacturing Initiative, Alan Weber, Alan Weber & Associates, Inc.
Front End of Line
INTRODUCTION: Front End of Line :: Download the new issue now!
Scaling pushes lithography to be able to print smaller and smaller patterns. Cleverness and deep understanding of the optics laws helped to achieve unthinkable results like printing features whose size is below the exposure wavelength.
Michael Brillouët, CEA-Leti
Profile: Nikon :: Download the new issue now!
Nikon Corporation
A Simple Model of Line-Edge Roughness :: Download the new issue now!
An attempt to develop a comprehensive stochastic model for LER based on deriving approximate expressions for the variance and correlations that occur at each step in the lithography process.
Chris Mack, Lithoguru.com
Back End of Line
INTRODUCTION: Back End of Line :: Download the new issue now!
In continuing Future Fab International articles on 3-dimensional integration (3Di), the following two articles mark recent progress on critical 3Di concepts and elements at CEA-Leti and SEMATECH.
Daniel C. Edelstein, IBM T.J. Watson Research Center
TSV-3D Activities at CEA-Leti :: Download the new issue now!
A brief overview of where CEA-Leti is today regarding TSV development and how it relates to Leti's global 3D activities.
Mark Scannell, CEA-Leti
Recent Advances in Submicron Alignment 300 mm Copper-Copper Thermocompressive Face-to-Face Wafer-to-Wafer Bonding and Integrated Infrared, High-Speed FIB Metrology :: Download the new issue now!
A report on recent advances in submicron alignment for 300 mm thermocompressive fave-to-fave Cu bonding and related metrology development to enable bond/align process feedback.
W.H. Teh, SEMATECH (Intel Assignee), 3D Interconnect , C. Deeb, ISMI (Intel Assignee), Metrology , J. Burggraf, EV Group, Austria, M. Wimplinger, EV Group, Austria, T. Matthias, EV Group, Austria, R. Young, FEI Company, C. Senowitz, FEI Company, A. Buxbaum, FEI Company
Metrology, Inspection & Failure Analysis
INTRODUCTION: Metrology, Inspection & Failure Analysis :: Download the new issue now!
In my professional life, I have read many technology papers that start with the words "The continuous shrinking of chip dimensions…" (drat! I myself wrote some of them!). What may have appeared a rhetorical expedient to start an article, in recent years has become the curse of the technology improvement.
Davide A. Lodi, Numonyx
In-line Process Variance Monitoring of Advanced 3D TSV Production Lines :: Download the new issue now!
How to control future 3D SIC production lines – getting data from 100 percent of the wafers and providing defect classification for yield management.
Nanda Tech
Wafer Fab & Packaging Integration
INTRODUCTION: Wafer Fab & Packaging Integration :: Download the new issue now!
Recent advancements in the packaging technology, namely in 3D chip stacking, have stimulated a tremendous growth toward the use of wafer-level processes for packaging integration. As a result, the traditional front-end and back-end segments of the IC industry have practically merged now (as far as process and equipment complexity goes) in the 3D-TSV area, and are ironically called by some of my colleagues at recent wafer-level packaging conferences "middle-end."
Christo Bojkov, Freescale Semiconductor
The European 3D Technology Platform (e-CUBES) :: Download the new issue now!
A description of a comprehensive 3D technology platform for future applications of heterogeneous system integration.
Peter Ramm, Fraunhofer IZM (et al.)
Assembly Test & Packaging Technologies
INTRODUCTION: Assembly Test & Packaging Technologies :: Download the new issue now!
The following paper by Lee Smith of Amkor gives some of the background and history behind the different types of stacked die and packages that have been utilized by the different designers to allow the overall size reduction and to increase performance of a product.
Steve Greathouse, Plexus Corporation
Achieving the 3rd Generation From 3D Packaging to 3D IC Architectures :: Download the new issue now!
A summary of the role industry collaboration played in enabling the first two generations of 3D packaging architectures.
Lee Smith, Amkor Technology Inc.
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