In this issue:
Future Visions & Current Concerns
 Introduction Download the new issue now!
“The best way to predict the future,” it has been said, “is to invent it.” Such is the case with manufacturing, which relies on ongoing innovation to enable advancements in reliability, efficiency and cost.
Alain E. Kaloyeros, CNSE
Moore’s Law, Madmen and Economists Download the new issue now!
The economist Kenneth Boulding is famously quoted as saying “Anyone who believes exponential growth can go on forever in a finite world is either a madman or an economist.” So engineers who are neither obviously mad nor practitioners of the “dismal science” have learned to live with the surprising longevity of Moore’s Law with what amounts to an intellectual shrug of the shoulders. This is highly rational behavior, since history has shown that predicting the end of Moore’s Law is essentially not at all cool.
Phillip Christie, imec
Thought Leadership Profile - Total Facility Solutions Download the new issue now!
Over the past two years, the semiconductor manufacturing industry has faced significant challenges in order to meet the demanding technology curve of Moore’s Law as well as the constraints of the consumer market.
Total Facility Solutions Business Development, Total Facility Solutions
Lithography 2020: Top Down Vs. Bottom Up Download the new issue now!
As the costs of lithography continue to escalate for future generations, a viable and complementary alternative is emerging in the form of directed self-assembly (“DSA”). In lithography, all the information for the patterning is transmitted “top down” from the mask, but cost scales with complexity. The DSA approach uses a “bottom up” chemical approach, similar to that used in nature, to drive complexity with a potentially compelling cost of ownership. This article reviews the opportunity and current status of the work.
Geoff Wild, AZ Electronic Materials
Chip Architecture & Integration
Introduction Download the new issue now!
One of the key lessons from the industrial revolution was that standardization enables markets to grow at explosive rates. Standardization radically altered the landscape of transportation (standard railroad gauges), warfare (interchangeable parts in Winchester rifles) and production (Henry Ford’s assembly line). Indeed, even the distribution method of electricity involved a pitched battle between Nicola Tesla (AC) and Thomas Edison (DC) as to what standard would be adopted for the power grid we still use today.
IPextreme
Semiconductor IP Standards: More Important Than You Think Download the new issue now!
Standards are abundant in today’s world, and they are quite diverse. There are standards for health and safety, standards for measurement and even standards for human behavior. The type of standard that is most apparent in the semiconductor industry is the technical standard.
Karen Bartleson, Synopsys
Manufacturing: Fab, Systems & Software
Introduction Download the new issue now!
In the design and implementation of manufacturing control systems, it can be said that there has been an appreciation for the need to understand the functionality to be delivered by those solutions. As continued development of factory automation progresses to more integrated and holistic fab solutions, however, there is commensurate need to understand the effect of a given solution on the overall manufacturing environment.
Thomas Sonderman, GLOBALFOUNDRIES
Thought Leadership Profile – CyberOptics Download the new issue now!
The days of taking manual measurements to obtain data about your semiconductor equipment and processes is over. Committed to innovating measurement technology™, CyberOptics Semiconductor offers a wireless set of advanced measurement solutions for leveling, gapping and teaching semiconductor equipment.
CyberOptics
Advanced Process Control Goes Manufacturing: APCM Conference in Europe Download the new issue now!
Manufacturers, suppliers and the scientific communities of semiconductor, photovoltaic, LED, flat panel, MEMS and other relevant industries are invited to the 12th European Advanced Process Control and Manufacturing conference, taking place at MINATEC Grenoble on April 16-18, 2012. Beyond the established topics of equipment and process control on unit process and fab level, the new agenda also includes current challenges and future needs of manufacturing effectiveness.
Klaus Kabitzsch, Dresden University of Technology, Michael Klick, Plasmetrex GmbH, Andreas Steinbach, Von Ardenne Anlagentechnik , Alan Weber, Alan Weber & Associates, Inc.
Fab Simulation and Variability Download the new issue now!
Simulation, specifically discrete event simulation, is widely employed throughout the manufacturing sector – particularly in semiconductor and photovoltaic fabs – for prediction and assessment of factory performance. Of special interest is fab cycle time and capacity. Whether it be a proposed, ramping or mature fab, it is vital to have accurate estimates of facility performance. Conventional wisdom among simulation personnel is that – once a detailed fab simulation model has been developed – the model should be run for a period of one to possibly two years of simulated time so as to reach the “steady state” performance of the simulated fab. This process is repeated a number of times and the average of the results are employed in the decision-making process (e.g., should more or fewer tools be used?). Again, conventional wisdom holds that such a process is sufficient to establish accurate estimates of fab performance. That assumption is challenged in this paper.
James P Ignizio, The Institute for Resource Management, Hernando Garrido, Fresenius Medical Care
Lithography Landscape
Introduction Download the new issue now!
This article provides compelling indirect justification regarding the strategic need for new families patterning materials and processes that augment and extend current methods. The success of extensible and manufacturable nanopatterning depends on approaches that circumvent or compensate for current lithographic limitations. The path forward must navigate through the apparent trade-off in conventional top-down lithography between three critical and interdependent chemically amplified resist performance factors: resolution, throughput and line edge roughness.
Daniel J.C. Herr, Joint School of Nanoscience and Nanoengineering/UNC−Greensboro
Section Sponsor - Nikon Download the new issue now!
Nikon Corporation has been one of the world’s leading optical companies for more than 90 years. Nikon developed the world’s first production-worthy step-and-repeat photolithography tool in 1980. Since then, over half of all integrated circuits printed have been manufactured on Nikon steppers and scanners.
Nikon Corporation
Optimum Dose for EUV: Technical vs. Economic Drivers Download the new issue now!
As EUV moves closer to insertion into pilot production, questions regarding cost-effectiveness take on increasing importance. One critical aspect is determining the optimum dose that balances cost-effective throughput vs. imaging performance. Due to EUV source power limitations, the tool manufacturers have specified very fast doses to meet their throughput targets. We will show how these low doses lead to shot noise problems and a resulting penalty in resist performance.
Moshe Preil, GLOBALFOUNDRIES
Front End of Line
Introduction Download the new issue now!
Low-power consumer electronics require fast circuit operation for demanding applications with complex functionality and low-power consumption for long battery life.
Didier Louis, CEA-Leti
Section Sponsor - Hitachi Download the new issue now!
Hitachi High Technologies, Inc. (HHT) is proud to introduce the semiconductor industry’s highest-volume production etch tool for critical and non-critical etch layers.
Hitachi High Technologies America, Inc.
The Challenge to Reduce Dissolved Oxygen for Advanced Processing Download the new issue now!
Controlling oxide formation on the wafer surface is one of the reasons for reducing residual dissolved oxygen (DO) levels in ultra-pure water as well as in dilute hydrogen fluoride. As the feature size in semiconductor manufacturing continues to decrease, the quality of water and the dissolved oxygen content are becoming increasingly more critical. For certain processes, a point-of-use deoxification step has become necessary. Challenges to decrease and maintain the low level of O2 will be discussed.
Christiane Gottschalk, ASTeX GmbH, a subsidiary of MKS Instruments
Though Leadership Profile - SAFC Hitech Download the new issue now!
Focused on customer intimacy and collaborative partnerships that deliver process improvements that meet and exceed customer needs, SAFC Hitech is a leading global materials and delivery systems supplier. From R&D partnerships with some of the world’s leading educational and research facilities to high-volume scale-up manufacturing, relationships are at the heart of our business.
SAFC Hitech
FDSOI for Next-Generation System on Chip Applications Download the new issue now!
The semiconductor industry has experienced extraordinary growth over the past several decades by shrinking feature dimensions for each generation of technology. This has enabled low-cost products and dramatically increased the speed and functionality of enterprise and consumer-based electronics applications. Conventional transistor scaling, however, has become very challenging, and researchers have thus looked to alternate device architectures to continue the scaling trend. Today’s SOC products require high performance with low power. FDSOI meets many of the requirements needed for future SOC applications.
Bruce Doris, IBM Research at Albany NanoTech, Kangguo Cheng, IBM Research at Albany NanoTech, Ali Khakifirooz, IBM Research at Albany NanoTech
Metrology, Inspection & Failure Analysis
Introduction Download the new issue now!
As integrated circuit features continue to shrink, interconnect lines, contacts and vias require characterization of the complete structure. Tomographic imaging provides a very useful means of viewing the 3D shape of these structures. Large features such as through silicon vias (TSVs) require X-ray methods.
Alain C. Diebold, CNSE
Advanced TEM Imaging Analysis Techniques Applied to BEOL Problems Download the new issue now!
In the last few decades, transmission electron microscopy has made enormous progress. Not only has the spatial resolution advanced far into the sub-Angstrom realm, but sophisticated new analytical methods have also been developed. This paper will show by means of three examples how this progress is used for back end of line characterization. First, we will show how 3D imaging using electron tomography allows the complete reconstruction of nano-meter-sized interconnect structures in the memory of a desktop computer. Secondly, low-dose spectroscopy and subsequent noise reduction is shown to allow characterization of radiation-sensitive intermetal dielectrics. Third, STEM imaging in a special electron-optical alignment is demonstrated to allow unprecedented Cu grain imaging in interconnects, enabling determination of grain size distributions with hitherto unseen precision.
Frieder H. Baumann, IBM Microelectronics Division
Wafer Fab & Packaging Integration
Introduction Download the new issue now!
3D integration is much more than the drilling and filling of TSVs …
Peter Ramm, Fraunhofer EMFT
3D Hyper-Integration: Past, Present and Future Download the new issue now!
Three-dimensional (3D) hyper-integration has recently been recognized as an emerging technology to lead to an industry paradigm shift due to its tremendous benefits. The concepts of 3D integrated circuits were conceived almost five decades ago. Worldwide academic and industrial research and development were actively conducted in the last decade; products and prototypes toward volume production have been demonstrated. Wide adoption still faces major technical and business challenges, but it holds a promising future for smart-systems applications.
James Jian-Qiang Lu, Rensselaer Polytechnic Institute
Assembly, Test & Packaging Technologies
Introduction Download the new issue now!
Electronic devices like smartphones and mobile devices require IC packages that are small and thin in order to meet consumer demands for more functionality within an increasingly limited space.
William T. Chen, ASE (U.S.) Inc.
Design for Board-Level Reliability Improvement in eWLB Packages Download the new issue now!
eWLB (embedded wafer-level BGA) is a key advanced package because of the advantages of higher I/O density, process easiness and integration flexibilities. It facilitates integration of multiple dies vertically and horizontally in one package without using substrates. Thus, recently eWLB development is moving forward to the next-generation packages of 3D integrations to meet the market demands. eWLB consists of diverse materials and structures built in a reconstituted wafer. As the volume increases, structural design as well as selection of materials becomes more important in determining process yield and long-term reliabilities. Therefore, it is necessary to investigate the key design factors affecting the reliability comprehensively. In this paper, the influences of materials characteristics and structural designs on the board-level reliability will be demonstrated. Since the requirements for improving performances of drop and thermal cycling on boards are sometimes a trade-off, it is important to find the optimal design parameters to meet both reliability performances. Therefore, constructive analysis has been performed by examining every design factor both in a component level and in a board level. The reliability study was carried out in depth by experimental approaches as well as through thermomechanical simulations. As a result, the most influential factors for reliability turned out to be relevant to the solder joint design, such as solder compositions and dielectric mechanical properties. On the other hand, the different structural design allows the life to be prolonged by providing increased resistance to the crack propagation and also by making the entire package body more flexible.
Won Kyoung Choi, STATS ChipPAC Ltd , Yaojian Lin, STATS ChipPAC Ltd , Chen Kang, STATS ChipPAC Ltd , Seng Guan Chow, STATS ChipPAC Ltd , Seung Wook Yoon, STATS ChipPAC Ltd , Pandi Chelvam Marimuthu, STATS ChipPAC Ltd
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